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Dołączył(a): poniedziałek, 16 sty 2012, 23:11
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Ciekawe rozważania dla interesujących się hardware AmigOne.


http://amigaworld.net/modules/newbb/vie ... r=0#811727

--- Copy & Paste ---

arthoropod :

All of this is a moot point as PPC development is dead at NXP.
This is no longer speculation, although you might consider it a rumor as I'm not able to tell you how I learned about it, but it was from someone that NXP has a relationship with.

And the gist of our conversation is that John Arends, the director of the Systems and Architecture, Networking and Multimedia Group at NXP Semiconductors, has stated that there will be no further development of the PPC at NXP.

They obviously still support their current products, and they have long term support programs that will keep some existing products available for some time to come.

Good news since I'm relying on NXP as a supplier on T2080 cpus. And Trevor will obviously still requires P5020, P5040, and P1022 processors.
And there are some much better processors available if we ever get SMP support, like the e6500 cored T4240 (the "big brother" of the processor we are planning to use in the T2080 laptop).

I could still vent at the major mistake in basing a system on the P1022. BUT I know who the real driving force is behind the creation of your new hardware is as I've know Paul Gentle at Varisys since before it was announce that Varisys had designed the X1000.

At one time I was in contact asking him advice on a revision I was making to Freescale's MPC8640 reference design board. Thanks in part to Paul, I substituted an AMD SB600 southbridge for the ULi component used in the original design.
I still have the docs for that project but I dropped it when I saw the specs for the X1000,
I wasn't initially sure that Varisys was involved in the X1000's development (Paul never told me), but I did know that his company was one of the few with experience designing products using the PA6T...and once I saw detailed photo of the X1000 and located the SB600...

However, even when I was working on my project and unbeknownst to me Paul was working on the X1000, Paul was discouraging people from using the PA6T in new designs.
Apple had purchase P.A. Semi, and was committed to supplying existing customers of the PA6T with components for a period of time (after all, some of the users were military contractors).

But Apple limited purchases to existing customers. And if Varisys hadn't been a previous customer, and purchased the cpus for Aeon, the X1000 project never would have happened.

Using the PA6T something Trevor wanted the X1000's design as the X1000 is basically a slightly improved variant of a system commission by Bill McEwen from Ack Systems. Doubt me, and I can provide you the specs and the original announcements.
Paul's design feature some improvement, but he clearly stated to me at the time that new designs should probably be based on Freescale's Qorlq family of PPC communications oriented processor.

The e5500 core hadn't been introduced yet, so that probably would have been an e500 cored cpu, but hopefully an e500mc cored cpu would have been used (if Paul had had his way) not one of the low cost e500v1 or v2 variants designed for the embededed market.
Anyway, after the remaining supplies of PA6T cpus reached to $500-600 level (Trevor absorbing the price increases out of his own pocket) and successor was obviously needed.
Ben Herman's was no longer part of the company and many of us that had heard about the announcement for the P5020 and P5040 pushed for that (and no doubt it was just what Paul would have preferred).
Its a good product, but our experiments with the e5500 and e6500 have uncovered one flaw, the memory controller produces pretty awful throughput .
How bad? Well a DDR2 based X1000 has much better memory bandwidth, and a DDR2 11,2 PowerMac is better still.
But there was no real way the anticipate that and its not a critical flaw, it just limits our memory transfers to about the level of a P4.

OK, on to Tabor, I believe this was in the works a long time ago, possible at the same time development started on the X5000, possibly before.
It could have used an e500mc cored cpu, but those cost several times what an e500v2 cpu costs.

And while I've stated over and over again that I would have preferred a 64 bit e5500 cored T10XX variant, which btw would not have significantly increased cost and would have had a few more PCI-E lanes, there's a simple fact that prevented that.

Those cpus weren't available during the A1222's development cycle. If that cycle was as early as I suspect, Tabor was essential finished at about the time these low cost variants of the e5500 core were introduced.

Still stings though, A Tabor board based on a T1024 could have bee 200 Mhz faster, 64 bit, with a better NIC, an superior PCI-e expansion capabilities.
A four core T1042 based model would have only been a few dollars more.
And both share the same basic core as the X5000, with standard fpu.
The similarities might have aided in porting OS'.

One other thing, Tabor will never have MorphOS support. The boards were offered years ago, and the idea of porting to a P1022, or any e500v2 based platform had been to rejected by MorphOS developers year ago. We'd discussed the e500 variants years ago, and rejected the idea of ever attempting a port to an e500v1 or e500v2 based cpu.

I don't actually blame this mess on Trevor, but Paul, as his primary market is Linux (he's not an Amigan, he's just a damned competent engineer), in the Linux world, you just use an spe orient math library, no big deal.
In our world, its not nearly that simple.

But I also still have faith in Paul Gentle, he knows where things are headed, and he won't lead Trevor into a blind alley.

Anyway, back to Power 9, the Talos II Lite and its potential ATX successor.
Sure the Talos II with only one cpu and the Talos II Lite on support one X16 and one X8 PCI-E slot
These slots are gen 4 though so they operate a two to four times the rate of Aeon boards.

Further, the X5000 and Tabor only supply four PCI-e lanes to there X16 video card slots.
And the combination of PCI-e slots and PCI slots on the X5000 is done with bridges and switches.
If your not familar with that idea, its why the SAM460 disables one expansion slot if you use the onboard SATA connectors.

But, a Talos II's X8 slot could use a riser or host card to divy up those 8 PCI-e lanes to service other slots.
Instead of one X8 PCIe slot, the lanes provided could supply one X4 slot, and four X1 PCI-E slots, and must I repeat again that they would operate at a much higher speed.

Also , what could a redesigned ATX board built around a single Power 9 cpu provide?
Well first the 16 lanes supplied to the Talos II's video slots could be separated into two groups of eight feeding two X16 slots this would still provide the same bandwidth as full X16 slots on a PCI-E 3.0 system.
Beyond that, are any of you aware how many systems provide less than 16 lanes to their video card slots. Many X64 systems only provide eight lanes, the X5000 provides four, Tabor also provides four, but those have the have the data rate of of the X5000.

So how does that equate? Well both the proposed X16 slots (using 8 PCI-E v4 lanes) on a Power 9 board would have four times the bandwidth of a Tabor video card slot (or eight times that of Tabor).
Taking into consideration that I an proposing two slots, that advantage grows to eight time the bandwidth of the X5000 and sixteen times the bandwidth of the A1222.

Then there are the eight lanes currently devoted to the PCI-E X8 slot. X8 cards aren't a common need by the average PC consumer, but if it were, well you'd just limit your self to one video card and install the X8 slot in the second X16 video slot.
Then the remaining 8 lanes could supply one X4 slot and four X1 slots .

That's seven expansion slots, with better throughput than most X64 systems, let alone available PPC system.

I think that's pretty good counter argument to the contention that Power 9 faces expansion limitations.
You forget, I know how many PCI-E lanes the SERDES channel of NXP's products can provide, and I can assure you its almost always less , at a much lower speed rate.

Oh, and btw, after an analysis the P1022 I still can't figure out how they are going to make it work without a bridge or switch.
The cpu only has six SerDes lanes. Four are shown connected to provide three PCI-E lanes (which does not make seen as three PCI-E lanes should only require three SerDes lanes, while a PCI-E X4 connection would require four SerDes lanes) we'll find out what that is all about when we see the boards.
But there is a small possibility that Tabor may only have a X3 connection to its video slot, not four, and either way, a slow connection.
That leaves two PCI-E lanes, and I'm unsure two is adequate to provide two port SATA 3.0 interface, so it might be limited to SATA 2.0.
However, the diagrams also these last SerDes lanes also providing for 2x Gigabit Ethernet through the SGMII connection to the SerDes bus.

Basically, with only six PCI-E lanes, I can't see how the A1222/Tabor is going to function.
At least the P5020 in the X5000 has 18 SerDes lanes (three times as many).

The structure of the Power 9 cpu is harder to compare as all I/O, inter-connectivity, memory, PCI-E, and other devices are connected to a massive cross-switch that can provide up to a 7 TB transfer rate (although this is divided amongst the cores so now single cpu receives no where near that much data).

But the Power 9 four core that is the base cpu for the Talos II provides 24 PCI-E lanes to its expansion bus, and I am unsure if the devices on the board are connected via additional PCI-E lanes.

As SerDes lanes have a one on one relationship with PCI-e lanes, that gives the Power 9 cpu at least 6 more lanes than the P5020 (probably more), AND as SerDes lanes on the P5020 provide for more than PCI-E (including DMA, networking, SATA, and the Real Time Debuging module) this comparison might be unbalanced.

In favor of the P5020, SATA or SAS requires connection of a controller board on the Power 9 system.
In favor of the Talos II, its board incorporates two Marvell Gigabit ethernet contollers that are no doubt connected via PCI-e lanes that don't service the expansion bus OR they are connected via something more advanced.
And beyond PCI-E, Power 9 has an expansion system called CAPI, and another link developed in cooperation with Nvidia called NVLink2.

Oh, and if you feel limited by the four thread per core Power 9 variants (refereed to as SMT4), there is an 8 thread per core variant referred to as SMT8.

SO, I honest don't care WHAT you THINK, these are the facts. And PPC? Its over.

Time to consider evolution or extinction.

Either way my favorite NG OS' will survive, and OS4? Hey a lot of the community doesn't hold it in the warmest regard anyway.
Many would just prefer to continue to develop "real" AmigaOS, and build on legacy designs.
If OS4 fails, they won't miss you.

Oddly, I will, I think competition drives innovation, and you're recruiting some damned fine coders like my friend Han de Ruiter.

But make no mistake, its time for all of you (and Hyperion and Aeon) to put your thinking hats on.

Personally, I don't care if you don't want to follow me to Power 9, and I'll be able to run your code with or without your permission (the same goes for MorphOS). And, I should also be able to emulate an X64 platform for the next fork of MorphOS, also my first project on obtaining a Talos II Lite will be a port of AROS.

So sit there with your smug sense of hubris and ignore the fact that the light at the end of your tunnel is the train of obsolescence steaming toward you at a steady pace.

You've already made one stupid miscalculation embracing low performance, incompatible e500v2 based hardware. The most powerful announced system, the X5000/40 isn't available, and you don't have support for SMP (making using the more powerful e6500 cored cpus relatively pointless).

Hey, on the bright side, if your lucky, maybe OS4.2 will enabled you to use the second core on your dual core systems before the cpus your systems are based on are eol'd.


--- End ---


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PostNapisane: niedziela, 20 maja 2018, 23:38 
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Dołączył(a): wtorek, 17 sty 2012, 21:57
Posty: 747
A co widzisz w nich ciekawego?
Hipotetyczny sprzęt, którego ogarnięcie (jednego rdzenia) przy obecnych możliwościach potrwałoby lata.

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PostNapisane: poniedziałek, 21 maja 2018, 06:59 
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Dołączył(a): poniedziałek, 16 sty 2012, 23:11
Posty: 1176
Przemek napisał(a):
A co widzisz w nich ciekawego?
Hipotetyczny sprzęt, którego ogarnięcie (jednego rdzenia) przy obecnych możliwościach potrwałoby lata.


W tym tekście dla mnie były ciekawe informacje o AmigaONE X1000 i X5000 a wypłynęły tylko w kontekście Talosa II.
Nie wymieniłbym X1000 czy X5000 na TalosaII bądź dowolną platformę z jabuszkiem.


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PostNapisane: poniedziałek, 21 maja 2018, 08:02 
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Dołączył(a): wtorek, 17 sty 2012, 21:57
Posty: 747
Rozumiem, a czemu byś nie wymienił?

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PostNapisane: poniedziałek, 21 maja 2018, 11:09 
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Dołączył(a): poniedziałek, 16 sty 2012, 23:11
Posty: 1176
Przemek napisał(a):
Rozumiem, a czemu byś nie wymienił?


Płyty X1000/X5000 zostały zaprojektowana od zera przez inżynierów Varisys na zlecenie A-Eon z założeniem, że docelowymi systemami mają być AmigaOS i Linux. Developerzy mają pełny dostęp do dokumentacji, nie są zależni od osób trzecich. Trevor konsultował prace z Hyperionem który również doradzał w projektowaniu. Czyli zero niespodzianek ... takich jak Genesi vs MaiLogic o mostek w płytach Teron i AmigaOne.

Technicznie elementy użyte do produkcji AmigaOne są najwyższej jakości: wielowarstwowy laminat, kondensatory, etc
Mając taką płytę w reku naprawdę widać porządne wykonanie -to nie jest chińczyk :)

Jedyny mankament to ... ograniczone zasoby ludzkie ... a doba ma tylko 24 godziny.


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